OSU8 Xilinx Implementation

Thoughout these schematics, the green blocks are links to their lower level schematics. Individual gates and flip-flops do not have schematics under them, because they are the primitive elements for Xilinx place-and-route, and for the ViewSim gate-level simulation.

Lower Schematics

• OSU8 Core - This is the main schematic for OSU8
• Address Decode