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OSU8 Microprocessor
Schematic
OSU8 Core
P1 Pointer
2:1 Mux
OSU8 Microprocessor
Overview
CPU Programming
Hardware Info
Schematic
Xilinx Implementation
Address Decoder
OSU8 Core
Normal Size
Large Size
8-Bit Data ALU
16-Bit Addr ALU
Control State Machine
State Register
Bus Control
Accumulator
B Register
Status Bits
Operand Register
Program Counter
Stack Pointer
P1 Pointer
Register
2:1 Mux
P2 Pointer
16-Bit Equals
Temp Register
8-Bit Zero
Buffers
Full Hierarchy Index
Implementation
Download Files
2-input MUX
The
P1 Pointer's 16-bit register
uses this 2-input MUX to allow it to load P1 from either of two sources.
OSU8: Simple 8-Bit Microprocessor Design; Paul Stoffregen
http://www.pjrc.com/tech/osu8/sch/my_mux2_reg16b_p1.html
Last updated: February 24, 2005
Status: These pages are a work-in-progress
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