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OSU8 Core Schematic
This is the main schematic for OSU8, which contains the complete
top-level view of the data paths, registers, logic and buffers.
Please refer to the
detailed description of the OSU8 Data Path,
for a description of how this circuitry is used to implement the
processors instructions.
Thoughout these schematics, the
green blocks are links to their
lower level schematics.
Individual gates and flip-flops do not have schematics under them,
because they are the primitive elements for Xilinx place-and-route,
and for the ViewSim gate-level simulation.
Also, view a much larger and more readable version
Lower Schematics
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Schematic
CPU Programming