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OSU8 Schematics, Complete List
- Xilinx Implementation
- Address Decoder
- OSU8 Core, also a Larger Image
- 8-bit ALU, All Data Operations
- 16-bit ALU, Address Computations
- Control State Machine Logic (Schematic in 8 sheets)
- Control State Machine State Register
- Bus Controller
- Accumulator Register
- B Register
- Status Bits
- Current Operand Register
- Program Counter
- Stack Pointer
- P1 Pointer
- P2 Pointer
- Equality Compare, 16 Bits
- Temporary Register, 16 Bits
- Tri-State Buffer, 8 Bits, ALU Output
- Tri-State Buffer, 8 Bits, Data Input
- Tri-State Buffer, 4 to 8 Bits, Operand to 8-Bit Bus
- Tri-State Buffer, 8 Bits, 16-Bit Bus LSB to 8-Bit Bus
- Tri-State Buffer, 8 Bits, 16-Bit Bus MSB to 8-Bit Bus
- Tri-State Buffer, 16 Bits, 8-bit Bus to 16D Bus
- Tri-State Buffer, 16 Bits, Program Counter to 16A Bus
- Tri-State Buffer, 16 Bits, Program Counter to 16C (Address) Bus
- Tri-State Buffer, 16 Bits, Stack Pointer to 16A Bus
- Tri-State Buffer, 16 Bits, Stack Pointer to 16C (Address) Bus
- Tri-State Buffer, 16 Bits, P1 Pointer to 16A Bus
- Tri-State Buffer, 16 Bits, P1 Pointer to 16C (Address) Bus
- Tri-State Buffer, 16 Bits, P2 Pointer to 16A Bus
- Tri-State Buffer, 16 Bits, P2 Pointer to 16C (Address) Bus
- Tri-State Buffer, 16 Bits, 16-Bit ALU to 16C (Address) Bus
- Tri-State Buffer, 16 Bits, 16C (Address) Bus to 16D Bus
- Pulldown, 8 Bits, Drives All Zeroes on 8-Bit Bus
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