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Teensy 4.0 Development Board
Teensy 4.0 is the latest Teensy, offering the fastest microcontroller and powerful peripherals in the Teensy 1.4 by 0.7 inch form factor.
Teensy 4.0 can be programmed using the Arduino IDE with Teensyduino add-on.
ProcessorTeensy 4.0 features an ARM Cortex-M7 processor at 600 MHz, with a NXP iMXRT1062 chip, the fastest microcontroller available today.
PinoutsTeensy 4.0 is the same size and shape as Teensy 3.2, and retains compatibility with most of the pin functions on Teensy 3.2.
Power Consumption & ManagementWhen running at 600 MHz, Teensy 4.0 consumes approximately 100 mA current.
Teensy 4.0 provides support for dynamic clock scaling. Unlike traditional microcontrollers, where changing the clock speed causes wrong baud rates and other issues, Teensy 4.0 hardware and Teensyduino's software support for Arduino timing functions are designed to allow dynamically speed changes. Serial baud rates, audio streaming sample rates, and Arduino functions like delay() and millis(), and Teensyduino's extensions like IntervalTimer and elapsedMillis, continue to work properly while the CPU changes speed.
Teensy 4.0 also provides a power shut off feature. By connecting a pushbutton to the On/Off pin, the 3.3V power supply can be completely disabled by holding the button for 5 seconds, and turned back on by a brief button press. If a coin cell is connected to VBAT, Teensy 4.0's RTC also continues to keep track of date & time while the power is off.
Teensy 4.0 also can also be overclocked, well beyond 600 MHz!
Cortex-M7 Processor DetailsARM Cortex-M7 brings many powerful CPU features to a true real-time microcontroller platform.
Cortex-M7 is a dual-issue superscaler processor, meaning M7 can execute 2 instructions per clock cycle, at 600 MHz! Of course, executing 2 simultaneously depends upon the compiler ordering instructions and registers. Initial benchmarks have shown C++ code compiled by Arduino tends to achieve 2 instructions about 40% to 50% of the time while performing numerically intensive work using integers and pointers.
Cortex-M7 is the first ARM microcontroller to use branch prediction. On M4, loops and other code which much branch take 3 clock cycles. With M7, after a loop has executed a few times, the branch prediction removes that overhead, allowing the branch instruction to run in only a single clock cycle.
Tightly Coupled Memory is a special feature which allows Cortex-M7 fast single cycle access to memory using a pair of 64 bit wide buses. The ITCM bus provides a 64 bit path to fetch instructions. The DTCM bus is actually a pair of 32 bit paths, allowing M7 to perform up to 2 separate memory accesses in the same cycle. These extremely high speed buses are separate from M7's main AXI bus, which accesses other memory and peripherals. 512K of memory can be accessed as tightly coupled memory. Teensyduino automatically allocates your Arduino sketch code into ITCM and all non-malloc memory use to the fast DTCM, unless you add extra keywords to override the optimized default.
Memory not accessed on the tightly coupled buses is optimized for DMA access by peripherals. Because the bulk of M7's memory access is done on the 2 tightly coupled buses, powerful DMA-based peripherals have excellent access to the non-TCM memory for highly efficient I/O.
Teensy 4.0's Cortex-M7 processor includes a floating point unit (FPU) which supports both 64 bit "double" and 32 bit "float". With M4's FPU on Teensy 3.5 & 36, and also Atmel SAMD51 chips, only 32 bit float is hardware accelerated. Any use of double, double functions like log(), sin(), cos() means slow software implemented math. Teensy 4.0 executes all of these with FPU hardware.
Memory is used in the following ways.
TODO: add examples here of code using FASTRUN, PROGMEM, F(), DMAMEM
RAM1 is accessed by 2 extremely high speed 64 bit buses, ITCM for running code, and DTCM for accessing data. For the highest possible performance, place code and variables in RAM1. Caching is not used with RAM1, because all location in RAM1 are accessed at the same speed as the M7 processor's caches.
RAM2 is accessed by a 64 bit AXI bus which runs at 1/4 of the CPU clock speed. While slower than ITCM & DTCM, it is still very fast. Normally data buffers and large arrays are placed in RAM2. The ARM Cortex-M7 data cache is used with this memory. When DMA transfers are used, the data cache management functions must be used to flush or delete cached data. DMA from peripherals can access RAM2 without competing with the extremely high bandwidth usage of RAM1 by the ITCM & DTCM buses.
Flash is accessed by FlexSPI, which maps the entire Flash into the M7's memory. Any location in the Flash chip may be read as if it were ordinary memory. Caching is used, so often there is little performance loss. But a cache miss does require many clock cycles to fill a cache row from the Flash chip. Normally only large tables, startup code, and other resources which are not speed critical should be accessed from the Flash memory. String constants may be placed only in the flash using F("string") syntax.